Cascade is the commercial face. FPGA is the technical moat. They are not two products competing for the flagship slot — they are two layers of the same architecture deployed across different timescales. The soft layer is ready now. The hard layer is being built toward.
Cascade is the flagship product. FPGA is the flagship technology. Lead with the product; defend with the technology.
Neither is more important. They serve different functions on different timescales. The question is sequencing.
| Dimension | Cascade | FPGA |
|---|---|---|
| Verticals | Cross-vertical — compliance, finance, dev tools, healthcare | Vertical — defense, aerospace, medical devices |
| Demo | 30 seconds — python -m manager.demo, HMAC + Ed25519 + SOC2 PASS |
Requires physical rig + Pi 5 + 30 minutes to explain |
| Deployment | docker compose up |
Hardware procurement |
| Iteration speed | Fast — 3 build rounds, 26 agents, new primitives in days | Slow — FPGA synthesis cycles are hours; hardware is fixed silicon |
| Test coverage | 314/315 tests + 4 documented falsification experiments | Bench-test data exists but not packaged for buyers |
| Patent defensibility | Patents #47/53/55/57/66/68 — behavioral governance, receipt chains, compliance-as-code | Patent #22 (WPT) + hardware-method patents — physically unique to WHL stack |
| Buyer timeline | Today — enterprises wanting AI compliance infrastructure exist now | 2028–2030+ — when regulators mandate hardware-enforced AI governance |
| Revenue model | SaaS subscription + compliance audit + per-tenant attestation | Chip licensing or specialized hardware integration |
| Pitch readiness | Fundable now — enterprise AI infrastructure is a current investment thesis | Pre-market — the regulatory environment hasn't caught up yet |
Choosing Cascade as the commercial face is not a relegation of the FPGA work. It is an acknowledgment that the two substrates serve different strategic functions — and the hardware substrate's function is foundational, not immediate.
Today Cascade's gate predicate is software-enforced (Python). In 2027, that predicate executes in FPGA silicon — physically enforced. Same architecture, two substrates. Cascade plus FPGA = "AI safety as physical impossibility." That is the strongest version of the thesis, and it only exists because the FPGA work is already done.
Patent #22 and the hardware-method patents are physically unique to the WHL stack. Software patents are powerful but software is more easily reimplemented — a well-funded competitor can approximate Cascade's software architecture. They cannot replicate a validated FPGA governance substrate that took years of bench work.
Defense, medical devices, aerospace, and eventually frontier AI will require hardware-enforced governance — not software promises. When that regulatory requirement crystallizes (and it will), WHL's FPGA work is years ahead of any competitor starting from scratch. The head start compounds.
Every primitive proved in silicon — admissibility checking, thermal monitoring, spectral analysis — maps to Cascade's software architecture. The FPGA work did not produce a separate product. It produced the physical proof of the same architectural claims that Cascade makes in software. That is not waste. That is cross-layer validation.
The roadmap is not a plan to replace one substrate with the other. It is a plan to integrate them — soft layer first, then hardware bridge, then hardware-rooted as the regulated standard.
Different audiences need different entry points into the same architecture.
Software, demoable in 30 seconds, fundable on today's enterprise AI thesis, cross-vertical, deployable. Then mention FPGA as the differentiator:
The FPGA work is not under the same kind of empirical pressure — it is already bench-validated. The gap is packaging: the bench data exists but is not yet assembled into a buyer-facing format. That is a documentation and communication problem, not a technical one.
"Cascade alone is software-enforced admissibility. With the FPGA layer underneath, it becomes hardware-enforced — the only AI governance stack defensible in regulated industries."
One architecture. Two substrates. Soft layer ships first. Hard layer is already built. The convergence is a product roadmap, not a research project.
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